Design engineers design integrated circuits (IC's, e.g. application specific integrated circuits (ASICs) or systems on chips (SOCs)) by transforming logical or circuit descriptions of the IC's into geometric descriptions, called layouts. IC layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with signal pins, and (2) interconnect lines (i.e., geometric representations of signal wiring) that connect the signal pins of the circuit modules.
Each IC also contains a power grid structure that provides power and ground to each electronic and circuit component of an IC. Each electronic or circuit IC component has a power pin(s) and a ground pin that is connected to the power grid structure. Power grid structure components include stripes, rails, and vias which must be of a certain strength (i.e., size) to meet design specifications (i.e., minimum specifications that the power grid structure must meet in order to be acceptable for use in the IC).
To create layouts and to physically implement these designs, design engineers typically use electronic design automation (“EDA”) applications or tools. Such tools can include floorplanning tools that assign sub-chips or blocks of circuit modules in the design to target layers and regions of the IC. Typically, each sub-chip or block requires its own power domain and power grid. Usually, a designer needs to code the power grid for each sub-chip (block), which could number more than 100 blocks for a single IC, and so a designer would need to manually generate more than 100 separate and unique routines. If any changes are required to any portion of a power grid, these changes must also be done manually and for the entire grid. Existing software in the industry allows only uniform one-size-fits-all distribution of power grid, and lacks the capability to dynamically reconfigure the power grid with any desired changes. Accordingly, in view of these and other problems, improvements are needed.
SUMMARY
The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.